| http://dbpedia.org/ontology/abstract
|
时序收敛（英語：Timing closure）是现场可编程逻辑门阵列、特殊應用積體電路等集成电路设计过程中，调整、修改设计，从而使得所设计的电路满足时序要求的过程。为了完成上述过程，工程师常常需要在电子设计自动化工具辅助下工作。“时序收敛”一词有时也用于表达这些要求最终被满足的状态。
, The Timing closure in VLSI design and elec … The Timing closure in VLSI design and electronics engineering is the process by which a logic design of a clocked synchronous circuit consisting of primitive elements such as combinatorial logic gates (<a href="/wiki/AND_gate" title="AND gate">AND</a>, <a href="/wiki/OR_gate" title="OR gate">OR</a>, <a href="/wiki/Inverter_(logic_gate)" title="Inverter (logic gate)">NOT</a>, <a href="/wiki/NAND_gate" title="NAND gate">NAND</a>, <a href="/wiki/NOR_gate" title="NOR gate">NOR</a>, etc.) and sequential logic gates (flip flops, latches, memories) is modified to meet its timing requirements. Unlike in a computer program where there is no explicit delay to perform a calculation, logic circuits have intrinsic and well defined delays to propagate inputs to outputs.ned delays to propagate inputs to outputs.
|
| http://dbpedia.org/ontology/wikiPageExternalLink
|
https://web.archive.org/web/20070228233817/http:/www.synopsys.com/products/logic/design_compiler.html +
, http://phy-tc.com/docs_timingclosure.html +
, http://www.cadence.com/products/digital_ic/rtl_compiler/index.aspx +
, http://www.cadence.com/products/digital_ic/soc_encounter/index.aspx +
, https://www.plunify.com/en/intime/ +
, https://web.archive.org/web/20070206065723/http:/www.synopsys.com/products/iccompiler/iccompiler.html +
, http://www.magma-da.com/Pages/BlastCreate.html +
, http://www.magma-da.com/Pages/blastfusion.html +
|
| http://dbpedia.org/ontology/wikiPageID
|
7024370
|
| http://dbpedia.org/ontology/wikiPageLength
|
5400
|
| http://dbpedia.org/ontology/wikiPageRevisionID
|
1122754300
|
| http://dbpedia.org/ontology/wikiPageWikiLink
|
http://dbpedia.org/resource/Asynchronous_circuit +
, http://dbpedia.org/resource/Electronic_design_automation +
, http://dbpedia.org/resource/Synchronous_circuit +
, http://dbpedia.org/resource/Machine_learning +
, http://dbpedia.org/resource/Category:Timing_in_electronic_circuits +
, http://dbpedia.org/resource/Design_closure +
, http://dbpedia.org/resource/Static_timing_analysis +
, http://dbpedia.org/resource/Placement_%28EDA%29 +
, http://dbpedia.org/resource/Physical_timing_closure +
, http://dbpedia.org/resource/Logic_synthesis +
, http://dbpedia.org/resource/Very_Large_Scale_Integration +
, http://dbpedia.org/resource/Electronic_engineering +
, http://dbpedia.org/resource/Clock_signal +
, http://dbpedia.org/resource/Sequential_logic +
, http://dbpedia.org/resource/Integrated_circuit_design +
, http://dbpedia.org/resource/Routing_%28EDA%29 +
, http://dbpedia.org/resource/Design_flow_%28EDA%29 +
|
| http://dbpedia.org/property/wikiPageUsesTemplate
|
http://dbpedia.org/resource/Template:Technical +
, http://dbpedia.org/resource/Template:Notes +
|
| http://purl.org/dc/terms/subject
|
http://dbpedia.org/resource/Category:Timing_in_electronic_circuits +
|
| http://purl.org/linguistics/gold/hypernym
|
http://dbpedia.org/resource/Process +
|
| http://www.w3.org/ns/prov#wasDerivedFrom
|
http://en.wikipedia.org/wiki/Timing_closure?oldid=1122754300&ns=0 +
|
| http://xmlns.com/foaf/0.1/isPrimaryTopicOf
|
http://en.wikipedia.org/wiki/Timing_closure +
|
| owl:sameAs |
http://rdf.freebase.com/ns/m.0h0vr6 +
, http://www.wikidata.org/entity/Q7806736 +
, https://global.dbpedia.org/id/4wo59 +
, http://dbpedia.org/resource/Timing_closure +
, http://zh.dbpedia.org/resource/%E6%97%B6%E5%BA%8F%E6%94%B6%E6%95%9B +
|
| rdf:type |
http://dbpedia.org/ontology/Election +
|
| rdfs:comment |
时序收敛（英語：Timing closure）是现场可编程逻辑门阵列、特殊應用積體電路等集成电路设计过程中，调整、修改设计，从而使得所设计的电路满足时序要求的过程。为了完成上述过程，工程师常常需要在电子设计自动化工具辅助下工作。“时序收敛”一词有时也用于表达这些要求最终被满足的状态。
, The Timing closure in VLSI design and elec … The Timing closure in VLSI design and electronics engineering is the process by which a logic design of a clocked synchronous circuit consisting of primitive elements such as combinatorial logic gates (<a href="/wiki/AND_gate" title="AND gate">AND</a>, <a href="/wiki/OR_gate" title="OR gate">OR</a>, <a href="/wiki/Inverter_(logic_gate)" title="Inverter (logic gate)">NOT</a>, <a href="/wiki/NAND_gate" title="NAND gate">NAND</a>, <a href="/wiki/NOR_gate" title="NOR gate">NOR</a>, etc.) and sequential logic gates (flip flops, latches, memories) is modified to meet its timing requirements. Unlike in a computer program where there is no explicit delay to perform a calculation, logic circuits have intrinsic and well defined delays to propagate inputs to outputs.ned delays to propagate inputs to outputs.
|
| rdfs:label |
Timing closure
, 时序收敛
|
