| https://dblp.org/rdf/schema#authoredBy
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https://dblp.org/pid/w/YuWang2 +
, https://dblp.org/pid/84/1781 +
, https://dblp.org/pid/94/1128 +
, https://dblp.org/pid/82/1107 +
, https://dblp.org/pid/39/721-4 +
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http://purl.org/net/nknouf/ns/bibtex#Inproceedings +
|
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https://dblp.org/pid/w/YuWang2 +
, https://dblp.org/pid/84/1781 +
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, https://dblp.org/pid/82/1107 +
, https://dblp.org/pid/39/721-4 +
|
| https://dblp.org/rdf/schema#documentPage
|
https://doi.org/10.1109/ISQED.2006.117 +
, https://doi.ieeecomputersociety.org/10.1109/ISQED.2006.117 +
|
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|
https://doi.org/10.1109/ISQED.2006.117 +
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https://dblp.org/db/conf/isqed/isqed2006 +
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5
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723-728
|
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https://doi.org/10.1109/ISQED.2006.117 +
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https://dblp.org/rec/conf/isqed/2006 +
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ISQED
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ISQED
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| https://dblp.org/rdf/schema#publishedInStream
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https://dblp.org/streams/conf/isqed +
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| https://dblp.org/rdf/schema#title
|
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization.
|
| https://dblp.org/rdf/schema#yearOfEvent
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2006
|
| https://dblp.org/rdf/schema#yearOfPublication
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2006
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https://doi.org/10.1109/ISQED.2006.117 +
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https://dblp.org/rdf/schema#Publication +
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Yu Wang et al.: Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization. (2006)
|
