https://dblp.org/rdf/schema#authoredBy
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https://dblp.org/pid/181/2815 +
, https://dblp.org/pid/47/6720 +
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, https://dblp.org/pid/94/6179 +
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https://dblp.org/rdf/schema#bibtexType
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http://purl.org/net/nknouf/ns/bibtex#Inproceedings +
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https://dblp.org/rdf/schema#createdBy
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https://dblp.org/pid/181/2815 +
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, https://dblp.org/pid/94/6179 +
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https://dblp.org/rdf/schema#documentPage
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https://doi.org/10.1109/ICPADS.2008.18 +
, https://doi.ieeecomputersociety.org/10.1109/ICPADS.2008.18 +
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https://dblp.org/rdf/schema#doi
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https://doi.org/10.1109/ICPADS.2008.18 +
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https://dblp.org/rdf/schema#listedOnTocPage
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https://dblp.org/db/conf/icpads/icpads2008 +
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https://dblp.org/rdf/schema#numberOfCreators
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5
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https://dblp.org/rdf/schema#pagination
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689-696
|
https://dblp.org/rdf/schema#primaryDocumentPage
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https://doi.org/10.1109/ICPADS.2008.18 +
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https://dblp.org/rdf/schema#publishedAsPartOf
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https://dblp.org/rec/conf/icpads/2008 +
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https://dblp.org/rdf/schema#publishedIn
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ICPADS
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https://dblp.org/rdf/schema#publishedInBook
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ICPADS
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https://dblp.org/rdf/schema#publishedInStream
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https://dblp.org/streams/conf/icpads +
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https://dblp.org/rdf/schema#title
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A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor.
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https://dblp.org/rdf/schema#yearOfEvent
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2008
|
https://dblp.org/rdf/schema#yearOfPublication
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2008
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owl:sameAs |
https://doi.org/10.1109/ICPADS.2008.18 +
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rdf:type |
https://dblp.org/rdf/schema#Publication +
, https://dblp.org/rdf/schema#Inproceedings +
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rdfs:label |
Xu Wang et al.: A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor. (2008)
|