https://dblp.org/rdf/schema#authoredBy
|
https://dblp.org/pid/121/1159 +
, https://dblp.org/pid/07/7663 +
, https://dblp.org/pid/41/575 +
, https://dblp.org/pid/27/0 +
, https://dblp.org/pid/18/7669 +
, https://dblp.org/pid/62/3571 +
|
https://dblp.org/rdf/schema#bibtexType
|
http://purl.org/net/nknouf/ns/bibtex#Inproceedings +
|
https://dblp.org/rdf/schema#createdBy
|
https://dblp.org/pid/121/1159 +
, https://dblp.org/pid/07/7663 +
, https://dblp.org/pid/41/575 +
, https://dblp.org/pid/27/0 +
, https://dblp.org/pid/18/7669 +
, https://dblp.org/pid/62/3571 +
|
https://dblp.org/rdf/schema#documentPage
|
https://doi.org/10.1109/ASICON47005.2019.8983480 +
|
https://dblp.org/rdf/schema#doi
|
https://doi.org/10.1109/ASICON47005.2019.8983480 +
|
https://dblp.org/rdf/schema#listedOnTocPage
|
https://dblp.org/db/conf/asicon/asicon2019 +
|
https://dblp.org/rdf/schema#numberOfCreators
|
6
|
https://dblp.org/rdf/schema#pagination
|
1-4
|
https://dblp.org/rdf/schema#primaryDocumentPage
|
https://doi.org/10.1109/ASICON47005.2019.8983480 +
|
https://dblp.org/rdf/schema#publishedAsPartOf
|
https://dblp.org/rec/conf/asicon/2019 +
|
https://dblp.org/rdf/schema#publishedIn
|
ASICON
|
https://dblp.org/rdf/schema#publishedInBook
|
ASICON
|
https://dblp.org/rdf/schema#publishedInStream
|
https://dblp.org/streams/conf/asicon +
|
https://dblp.org/rdf/schema#title
|
A Grain-Adaptive Computing Structure for FPGA CNN Acceleration.
|
https://dblp.org/rdf/schema#yearOfEvent
|
2019
|
https://dblp.org/rdf/schema#yearOfPublication
|
2019
|
owl:sameAs |
https://doi.org/10.1109/ASICON47005.2019.8983480 +
, http://dx.doi.org/10.1109/ASICON47005.2019.8983480 +
|
rdf:type |
https://dblp.org/rdf/schema#Publication +
, https://dblp.org/rdf/schema#Inproceedings +
|
rdfs:label |
Xinyuan Qu et al.: A Grain-Adaptive Computing Structure for FPGA CNN Acceleration. (2019)
|